1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device including a capacity plate, which adds a capacity to its memory cells in order to make the semiconductor memory device strong against a soft error. Moreover, the present invention relates to a semiconductor memory device in which a failed memory cell is replaced with a redundant memory cell.
2. Description of the Prior Art
In recent years, in a semiconductor memory device such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory) or the like, the quantity of charge for holding its memory has been gradually decreased by integration of an IC and decrease of the operating voltage of the IC. With this, such a phenomenon that held data may be easily changed (corrupt data occur) by affection of outer stresses such as cosmic rays etc. at the time of memory holding, namely, a soft error is easy to occur. Therefore, the semiconductor, which is strong against the soft error, is required.
Particularly, as to the SRAM in which a high resistance load type or TFT type memory cell is used, the tendency that the operating characteristic deteriorates is strong with reduction of power. Thus, in recent years, an SRAM, which uses a full CMOS type (bulk six transistors type) memory cell (hereinafter referred to “CMOS-SRAM”), has gradually become a main stream.
As shown in FIG. 12A, a memory cell of a CMOS-SRAM includes two n type bulk access transistors AT1 and AT2 (hereinafter referred to “access transistors AT1 and AT2” for short), two n type bulk driver transistors DT1 and DT2 (hereinafter referred to “driver transistors DT1 and DT2” for short), and two p type bulk load transistors LT1 and LT2 (hereinafter referred to “load transistors LT1 and LT2” for short).
The memory cell of the CMOS-SRAM is such that when the access transistors AT1 and AT2 are turned on by a signal which is inputted into the memory cell via a word line WL, unit information is written into or read out from first and second nodes N1 and N2 via bit lines BL and BL#. Since the CMOS-SRAM can charge the nodes N1 and N2 at the H level side by means of the load transistors LT1 and LT2, it has an advantage of excellent resistance to the soft error as compared with a high resistance type SRAM or a TFT type SRAM whose memory node has a weak charging power.
However, in the CMOS-SRAM also, the soft error has been becoming easy to occur since the stored charge (voltage×capacity) of the memory cell has been becoming smaller due to decrease of the operating voltage, integration of the device or fining of the cell size. Therefore, it is necessary to apply measures of some kind for the soft error. In addition, the soft error generally occurs by the fact that ionized electrons occur in a semiconductor substrate and near it due to outer stresses (for example, a rays or neutron rays) and thereby the ionized electrons change the charge level of H level at the nodes N1 and N2 to make the memory cell malfunction.
Hereinafter, an example of an aspect of occurrence of the soft error will be described with reference to FIGS. 12A and 12B and FIGS. 13A and 13B. FIG. 12A shows the state in which the memory cell holds a proper data. In this state, by the inverter latch, the first node N1 is held at H level (high level) while the second node N2 is held at L level (low level). In this case, the first node N1 is connected to a power voltage line VDD via the load transistor LT1 of ON state while the second node N2 is connected to a ground voltage line GND via the driver transistor DT2 of ON state.
When the charge by a rays instantaneously enters (collides) into the first node N1, as shown in FIG. 12B, the drive by the power voltage line VDD via the load transistor LT1 comes short so that the first node N1 is changed from H level to L level. When the first node N1 is changed to L level in this manner, as shown in FIG. 13A, the load transistor LT2 is turned to ON. As the result, the second node N2 is connected to the power voltage line VDD so that it is changed from L level to H level.
When the first node N1 is changed to L level, as shown in FIG. 13B, the load transistor LT1 is turned to OFF. As the result, the first node N1 is fixed to L level. Namely, it becomes the reverse state with the state shown in FIG. 12A, in which the first node N1 is held at L level while the second node N2 is held at H level, so that the error data is kept holding (soft error).
Moreover, in the semiconductor memory device such as the CMOS-SRAM, even if the memory cell can conduct memory hold operation properly, it sometimes causes a stand-by failure (stand-by current failure). Namely, for example, in the event that a slight electrical short circuit occurs in the memory cell of the CMOS-SRAM due to adhesion of debris or the like during the manufacturing process, there may occur such a phenomenon that a current flows by the slight short circuit, that is to say, a stand-by failure at the time of the stand-by mode, although it does not causes interference with memory holding operation. In this case, since the memory holding operation is properly performed, the memory cell in which the stand-by failure has occurred can be found by a normal examination prior to the shipment of the products, thereby it cannot be relieved. Therefore, there may occur such a problem that the yield is lowered. Of course, the stand-by failure is also promoted by decrease of the operating voltage or integration (fining of cell size) of the IC.
As the above-mentioned short circuit, for example, the following matters may be indicated.                (1) A short circuit between one node and the other node.        (2) A short circuit between the node and the power voltage line VDD.        (3) A short circuit between the node and the ground voltage line Vss.        (4) A short circuit between the node and the word line.        (5) A short circuit between the node and the bit line;        (6) A short circuit between the bit line and the word line.        (7) A short circuit between the word line and the power voltage line VDD.        (8) A short circuit between the bit line and the ground voltage line Vss.        (9) A short circuit between the power voltage line VDD and the ground voltage line Vss.        
On the other hand, in the semiconductor memory device with a mass storage capacity, generally, in order to improve the yield, there is provided redundant memory cell, which are to be replaced with the failed memory cell which does not properly operate. When the failed memory cell is found within the semiconductor memory device, the failed memory cell is replaced with the redundant memory cell. The operation to replace the failed memory cell with the redundant memory cell is conducted, for example, by the following steps.
Namely, at first, the address of the failed memory cell is specified or designated. Then, the fuse of the failed memory cell within the redundant program circuit is cut by laser or the like. Thus, the failed memory cell is held at a normally nonselective state to be nullified. After that, the address of the nullified failed memory cell is assigned to the redundant memory cell. In consequence, the nullified failed memory cell is replaced with the redundant memory cell.
Consequently, at first, it is necessary for the semiconductor memory device such as the CMOS-SRAM to provide a structure which can reduce occurrence of the soft error regardless of decrease of the operating voltage of the IC, integration of the IC or fining of the cell size of the IC.
Thus, there has been proposed an SRAM in which the storage capacity of a memory cell is increased by adding a capacity to memory nodes so as to reduce an soft error etc (for example, see U.S. Pat. No. 5,541,427, JP No. 6-302785A, JP No. 63-16658A). However, in the conventional SRAM disclosed in each of the above-mentioned prior art documents, in which the capacity is added to the memory nodes, there has been a problem that the structure and the manufacturing process thereof is complex.
Moreover, in the semiconductor memory device such as the CMOS-SRAM or the like, even if the stand-by failure can be reduced, it is difficult to prevent this perfectly. Accordingly, it is also necessary for the semiconductor memory device to provide a structure which can easily or simply replace the failed memory cell with the redundant memory cell when the stand-by failure has occurred in the memory cell.